During the keynote address at the Intel Developer Forum recently held in San Francisco, Intel CEO Paul Otellini displayed a silicon wafer containing the world's first working chips featuring 22nm transistor technology, which include both densely packed SRAM memory and logic circuits to be used in future Intel microprocessors.
Because of their low complexity, SRAM cells are a common benchmark used in the microelectronics industry to demonstrate technology performance and chip reliability of a new manufacturing process, before going on to design the much more complicated microprocessors and other logic chips.
The SRAM cells on the chips come in two kinds: one, with an area of 0.108 square microns, was optimized for low voltage operation, while the other, occupying a surface of only 0.092 square microns, was optimized for high density and is the smallest SRAM cell in a working circuit reported to this date.
The test chips each pack an outstanding 2.9 billion transistors (approximately twice the density of the previous 32nm generation) and an unprecedented 43.39 MB of SRAM in an area the size of a fingernail, confirming once more the validity of Moore's law well beyond the point where many industry experts thought manufacturing processes would hit an insurmountable wall.
To obtain such high transistor densities, technologies that were already in use for the 32nm process such as double patterning and immersion lithography were further refined. To name just one improvement, the 22nm transistors are patterned with exposure tools using light with a wavelength of 193nm, which is beyond the visible spectrum and transports higher levels of energy.
An Intel spokeswoman told us the company is targeting the second half of 2011 for the industrial production of these chips. After that, the next generation as specified by the International Technology Roadmap for Semiconductors (ITRS) will feature 16nm transistors, and will likely see a transition to nanoelectronics before the conservative industry estimate of 2018.
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