Researchers agree that chip manufacturers will soon reach a hard limit in terms of transistor miniaturization, disproving rule-of-thumb predictions that transistor density roughly doubles every 18 to 24 months. But a collaboration between IBM, Purdue University and the University of California in Los Angeles may have found a way to squeeze more transistor in the same area by building them vertically rather than horizontally.

The key to the researchers' discovery is the use of nanowires, tiny structures that can be produced with industry-standard lithography techniques and have the potential to perform much better than traditional silicon transistor, as the scientific community has known for some time.


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Despite taking up comparatively more space than nanowires, traditional transistors have been a preferred choice so far mainly because they are formed by so-called heterostructures, meaning each part is very precisely spatially confined, which improves the control over the flow of electrons traveling in it. Up to now, researchers weren't able to recreate the same kind of sharply defined structures in nanowires, but this new discovery paves the way to their more widespread application in the electronics industry.

The researchers elaborated a complex procedure to manufacture efficient nanowires: tiny particles of a gold-aluminum alloy were first heated and melted inside a vacuum chamber, and then silicon gas was introduced into the chamber saturating the mixture and causing the silicon to precipitate and form wires. Each wire was then covered with a liquid bead of gold-aluminum, making the structure resemble a mushroom. Finally, the chamber temperature was decreased allowing the structure to solidify, and germanium was deposited onto the silicon.

What's even more interesting about the process, the group commented in a paper published on the journal Science, is that it can be modified to produce different kinds of heterostructures, which allows scientists to experiment further and could provide a new method for creating small and efficient nanowire transistors.

The work was funded by the National Science Foundation through the Electronic and Photonic Materials Program.

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