Last year, a team of U.S. researchers applied the pruning shears to computer chips to trim away rarely used portions of digital circuits. The result was chips that made the occasional mistake, but were twice as fast, used half as much energy, and were half the size of the original. Now, building on the same “less is more” idea, the researchers have built an “inexact” prototype silicon chip they claim is at least 15 times more efficient than current technology in terms of speed, energy consumption and size.
In the traditionally exacting world of computing, it might seem counter intuitive to set out to develop a chip that is allowed to make a few errors. But by managing the probability of errors and restricting which calculations are allowed to produce errors, the research team led by Krishna Palem has been able to slash energy demands while also boosting performance.
In addition to removing certain processing components, the team also employed another innovation in the prototype chip to further cut energy demands called “confined voltage scaling,” which trades some performance gains by taking advantage of improvements in processing speed.
“In the latest tests, we showed that pruning could cut energy demands 3.5 times with chips that deviated from the correct value by an average of 0.25 percent,” said Avinash Lingamneni, a Rice graduate student and co-author of the study. “When we factored in size and speed gains, these chips were 7.5 times more efficient than regular chips. Chips that got wrong answers with a larger deviation of about 8 percent were up to 15 times more efficient.”
While you probably wouldn’t want to find any inexact chips in the cockpit of an airplane or a missile guidance system, there are plenty of applications where a certain margin of error is acceptable.
“Particular types of applications can tolerate quite a bit of error. For example, the human eye has a built-in mechanism for error correction,” says project co-investigator Christian Enz. “We used inexact adders to process images and found that relative errors up to 0.54 percent were almost indiscernible, and relative errors as high as 7.5 percent still produced discernible images.”
Palem says devices such as hearing aids, cameras and other electronic gadgets that use special-purpose “embedded” microchips are likely to be the first applications for the pruned processors.
The inexact design is also integral to the I-slate educational tablet being developed by the Rice-NTU Institute for Sustainable and Applied Infodynamics (ISAID). Intended for Indian classrooms where there is no power, the low-cost tablet is being designed to run on solar power from small panels like those found on solar-powered calculators by using pruned chips that cut power requirements in half.
Earlier this year, Indian officials in the Mahabubnagar District announced plans to put 50,000 I-slates into middle and hig school classrooms over the next three years. Palem expects the first I-slates, along with the first prototype hearing aids, to contain pruned chips will appear by 2013.
The research team, made up of experts from Rice University in Houston, Singapore’s Nanyang Technological University (NTU), Switzerland’s Center for Electronics and Microtechnology (CSEM) and the University of California, Berkeley, unveiled their prototype pruned chips at the ACM International Conference on Computing Frontiers in Calgliari, Italy, this week, where they picked up best-paper honors.
Source: Rice University
